2026-09-20T19:41:23Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81342 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Feng, Milton Seo, Dongwon 2015-09-25T20:10:39Z 2015-09-25T20:10:39Z 10000-01-01 2000 2000 A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions. Made available in DSpace on 2015-09-25T20:10:39Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9971188.pdf: 3742667 bytes, checksum: d27c015a310706bc1226e161264f1350 (MD5) Previous issue date: 2000 Embargo set by: Seth Robbins for item 82623 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 119 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000. http://hdl.handle.net/2142/81342 (MiAaPQ)AAI9971188 eng Engineering, Electronics and Electrical 1-Gs/s, 14-Bit Digital -to -Analog Converter and Track -and -Hold Amplifier text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.