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        <datestamp>2023-07-11</datestamp>
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          <dc:contributor>Hwu, Wen-Mei W.</dc:contributor>
          <dc:creator>Connors, Daniel Alexander</dc:creator>
          <dc:date>2015-09-25T20:10:40Z</dc:date>
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          <dc:date>10000-01-01</dc:date>
          <dc:date>2000</dc:date>
          <dc:date>2000</dc:date>
          <dc:description>This dissertation proposes and investigates four key architectural and compilation techniques that eliminate dynamic redundancy to improve the resource utilization and performance. The Reusable Computation Region Framework (RCRF) provides a compilation framework to accurately determine the regions, called Reusable Computation Regions (RCRs), of a program in which reuse is likely to occur. The Compiler-directed Computation Reuse (CCR) approach integrates compiler and architecture techniques to exploit execution behavior of these regions. In this approach, the Instruction Set Architecture (ISA) provides a simple interface for the compiler to communicate the run-time execution of each region into a hardware structure. The Dynamic Computation Management System (DCMS) enhances the effectiveness of the compiler-directed computation reuse approach by dynamically activating the statically-selected computation regions according to run-time program behavior. Finally, a class of computation regions formed by the RCRF can be exploited using compiler transformation and existing architecture support. In the compiler-based Value Optimization Framework (VOF), program reformulation and predicated execution-based value transformations are used to exploit the redundancy of regions. By systematically coordinating compiler techniques and hardware technologies significant amounts of the dynamic computation redundancy can be eliminated in program execution.</dc:description>
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  Previous issue date: 2000</dc:description>
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Lift date: Forever
Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
          <dc:description>Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
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          <dc:description>211 p.</dc:description>
          <dc:description>Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.</dc:description>
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          <dc:identifier>(MiAaPQ)AAI9989969</dc:identifier>
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          <dc:subject>Computer Science</dc:subject>
          <dc:title>Eliminating Dynamic Computation Redundancy</dc:title>
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            <department>Electrical Engineering</department>
            <discipline>Electrical Engineering</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
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