2026-09-19T15:47:07Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81347 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Polychronopoulos, Constantine D. Dimitriou, Georgios 2015-09-25T20:10:40Z 2015-09-25T20:10:40Z 10000-01-01 2000 2000 We tested MSWP on a Coral 2000 simulator, using several synthetic and SPEC benchmarks. The results we obtained encourage us to continue our research. In particular, we obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops with unpredictable branches. We also obtained a speedup of up to 15% on perl, a highly sequential SPEC95 benchmark, utilizing task-level speculation in an attempt to increase the available instruction-level parallelism. Made available in DSpace on 2015-09-25T20:10:40Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9989980.pdf: 11919804 bytes, checksum: f907dfa6a5df227b2b7387223f16866a (MD5) Previous issue date: 2000 Embargo set by: Seth Robbins for item 82628 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 226 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000. http://hdl.handle.net/2142/81347 (MiAaPQ)AAI9989980 eng Engineering, Electronics and Electrical Loop Scheduling for Multithreaded Processors text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.