2026-09-18T19:36:39Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81349 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

eng Naresh Shanbhag Goel, Manish 2015-09-25T20:10:41Z 2015-09-25T20:10:41Z 10000-01-01 2000 2000 We present a design methodology for low-power communication systems. This is based on the concept of DAT and intellectual property (IP) core generators. Energy-optimum parameters are obtained via DAT, and are fed into IP core generators, which generate a synthesizable VHDL description of the IP core. The IP cores are synthesized via commercial logic synthesis tools. The proposed design methodology has been applied to generate receiver gate-level netlist for several channels including the microwave and cable channels. Made available in DSpace on 2015-09-25T20:10:41Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9990006.pdf: 5335094 bytes, checksum: 73e01dece454dc6376ac503e219502ac (MD5) Previous issue date: 2000 Embargo set by: Seth Robbins for item 82630 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 116 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000. http://hdl.handle.net/2142/81349 (MiAaPQ)AAI9990006 Engineering, Electronics and Electrical Low-Power Reconfigurable Digital Signal Processing text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.