2026-09-19T18:59:49Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81355 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

109 p. Hajj, Ibrahim N. Lu, Ninglong 2015-09-25T20:10:42Z 2015-09-25T20:10:42Z 10000-01-01 2000 2000 At the logic hierarchical level, we have developed a logic-level timing analyzer that will perform static timing simulation as well m coupling noise estimation using the information produced during the circuit hierarchy stage. The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input. Made available in DSpace on 2015-09-25T20:10:42Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9990067.pdf: 4339793 bytes, checksum: 420448dcb86bd89425bae39c7a1c3cae (MD5) Previous issue date: 2000 Embargo set by: Seth Robbins for item 82636 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000. http://hdl.handle.net/2142/81355 (MiAaPQ)AAI9990067 eng Engineering, Electronics and Electrical Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects text Electrical Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.