2026-09-20T20:02:35Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81611 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

2015-09-25T20:19:31Z 2015-09-25T20:19:31Z 10000-01-01 2002 2002 Torrellas, Josep Solihin, Yan Alternatively, the memory can directly execute memory-intensive code sections. We propose a compiler and run-time algorithm to break out the code into sections with uniform memory and compute behavior. These sections are statically or dynamically mapped on the memory or the main processor based on their affinity. In addition, processor and memory overlap their execution as much as possible. We show that the resulting speedups are close and often higher than ideal speedups on a more expensive machine with two identical main processors. Made available in DSpace on 2015-09-25T20:19:31Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3070443.pdf: 5213852 bytes, checksum: 7d96ed4da4fa2116f89bc9aad3650f15 (MD5) Previous issue date: 2002 Embargo set by: Seth Robbins for item 82892 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 102 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002. http://hdl.handle.net/2142/81611 (MiAaPQ)AAI3070443 eng Computer Science Improving Memory Performance Using Intelligent Memory text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.