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oai:www.ideals.illinois.edu:2142/81643 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

U of I Only 168 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004. http://hdl.handle.net/2142/81643 2015-09-25T20:19:40Z 2015-09-25T20:19:40Z 10000-01-01 2004 2004 Chapters 6 and 7 address ECO problems. Chapter 6 presents two algorithms to resolve overlaps between power rails and signal wires which are introduced by power rail redesign. In chapter 7, we propose an algorithm to eliminate capacitive crosstalk violations. Made available in DSpace on 2015-09-25T20:19:40Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3131057.pdf: 8481118 bytes, checksum: c649978a91338afa404ca2ffe381f878 (MD5) Previous issue date: 2004 Embargo set by: Seth Robbins for item 82924 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Wong, Martin D.F. Xiang, Hua (MiAaPQ)AAI3131057 eng Engineering, Electronics and Electrical New Strategies for High Performance VLSI Physical Design text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.