2026-09-19T22:29:43Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81651 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Torrellas, Josep Renau, Jose 2015-09-25T20:19:42Z 2015-09-25T20:19:42Z 10000-01-01 2004 2004 Experiments with the SpecInt 2000 codes show that a CMP with 4 3-issue cores and support for SM delivers a speedup of 1.27 over a 3-issue superscalar. The SM CMP is even faster than a 6-issue superscalar at the same frequency, and consumes only 85% of its power. In fact, for the same average power in both chips, the SM CMP is 1.13 times faster than the 6-issue superscalar on average. Made available in DSpace on 2015-09-25T20:19:42Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3153411.pdf: 4584573 bytes, checksum: 88dbb3b6e4587f493f1a3712b9cccaa2 (MD5) Previous issue date: 2004 Embargo set by: Seth Robbins for item 82932 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 75 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004. http://hdl.handle.net/2142/81651 (MiAaPQ)AAI3153411 eng Computer Science Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.