2026-09-19T09:19:57Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81658 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

David Padua Sura, Zehra Noman 2015-09-25T20:19:47Z 2015-09-25T20:19:47Z 10000-01-01 2004 2004 The analysis techniques described are used in the implementation of a virtual machine that guarantees sequentially consistent execution of Java bytecodes. This implementation is used to show the effectiveness of our analysis algorithms. On many benchmark programs, the performance of programs on our system is close to 100% of the performance of the same programs executing under a relaxed memory model. Specifically, we observe an average slowdown of 10% on an Intel Xeon platform, with slowdowns of 7% or less for 7 out of 10 benchmarks. On an IBM Power3 platform, we observe an average slowdown of 26%, with slowdowns of 7% or less for 8 out of 10 benchmarks. Made available in DSpace on 2015-09-25T20:19:47Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3160959.pdf: 6999165 bytes, checksum: a25ecca2a0057a5473e8731667a497b3 (MD5) Previous issue date: 2004 Embargo set by: Seth Robbins for item 82939 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 139 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004. http://hdl.handle.net/2142/81658 (MiAaPQ)AAI3160959 eng Computer Science Analyzing Threads for Shared Memory Consistency text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.