2026-09-24T00:03:06Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81724 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Torrellas, Josep Nakano, Jun 2015-09-25T20:20:10Z 2015-09-25T20:20:10Z 10000-01-01 2006 2006 We show that FGBB should be applied in an architecture-aware manner, following the shapes of architectural modules. The reason is that architectural functionality affects the BB needed through temperature and type of critical path. To prove this idea, we develop a model of threshold voltage variation and apply it to simulated batches of chips. We show that architecture-aware FGBB enables 35% of the chips to work at the highest frequency, compared to 18% with conventional FGBB, potentially increasing each chip's value by 50%. It also reduces the leakage of the chips by 40%, compared to 25% with conventional FGBB. Made available in DSpace on 2015-09-25T20:20:10Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3223677.pdf: 2577497 bytes, checksum: 58b6f04b5813ca124a7ff4b22411e136 (MD5) Previous issue date: 2006 Embargo set by: Seth Robbins for item 83005 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 76 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006. http://hdl.handle.net/2142/81724 (MiAaPQ)AAI3223677 eng Computer Science Techniques to Address Unreliability and Variability of Computing Systems text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.