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Torrellas, Josep Sarangi, Smruti R. 2015-09-25T20:20:23Z 2015-09-25T20:20:23Z 10000-01-01 2007 2007 Using this model we introduce a novel framework that shows how microarchitecture techniques can mitigate variation-induced errors and even trade them off for power and processor frequency. Several such techniques are analyzed---in particular, a high-dimensional dynamic-adaptation technique that maximizes performance when there is slack in variation-induced error rate and power. The results show that our best combination of techniques increases processor frequency by 61% on average, allowing the processor to cycle 26% faster than without variation. Processor performance increases by 44% on average, resulting in a performance that is 18% higher than without variation---at only a 12.5% area cost. Made available in DSpace on 2015-09-25T20:20:23Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3270016.pdf: 4067323 bytes, checksum: 4df17f870c82d27d05e4a9aa6ae18a64 (MD5) Previous issue date: 2007 Embargo set by: Seth Robbins for item 83049 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 142 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007. http://hdl.handle.net/2142/81768 (MiAaPQ)AAI3270016 eng Computer Science Techniques to Mitigate the Effects of Congenital Faults in Processors text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.