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oai:www.ideals.illinois.edu:2142/81853 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Patel, Sanjay J. Mahesri, Aqeel A. 2015-09-25T20:20:42Z 2015-09-25T20:20:42Z 10000-01-01 2009 2009 We propose a methodology for performing an integrated optimization of both the micro-architecture and the physical circuit design of the cores and caches. In our approach, we use statistical sampling of the design space for evaluating the performance of the micro-architecture and RTL synthesis to characterize the area-power-delay of the underlying circuits. This integrated methodology enables a much more powerful analysis of the performance-area and performance-power tradeoffs for the low level micro-architecture. We use this methodology to find the optimal design points for an accelerator architecture under area constraints and power constraints. Our results indicate that more complex architectures scale well in terms of performance per area, but that the addition of a power constraint favors simpler architectures. Made available in DSpace on 2015-09-25T20:20:42Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3363030.pdf: 2644865 bytes, checksum: 18f0249fc7b497ab3b86cbd6b2032aab (MD5) Previous issue date: 2009 Embargo set by: Seth Robbins for item 83134 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 152 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009. http://hdl.handle.net/2142/81853 (MiAaPQ)AAI3363030 eng Computer Science Tradeoffs in Designing Massively Parallel Accelerator Architectures text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.