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Banerjee, Prithviraj Krishnaswamy, Venkatram 2015-09-25T20:20:51Z 2015-09-25T20:20:51Z 10000-01-01 1997 1997 We finally settled on a partitioning based approach to parallelization. This technique gives us acceptable speedups, if the partitioning and placement of partitions on processors is done carefully. Partitioning and placement issues are examined thoroughly in this thesis. Made available in DSpace on 2015-09-25T20:20:51Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9737169.pdf: 4867838 bytes, checksum: b306c1aaa2a3577b043c19f49d268c40 (MD5) Previous issue date: 1997 Embargo set by: Seth Robbins for item 83163 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 100 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997. http://hdl.handle.net/2142/81882 (MiAaPQ)AAI9737169 eng Engineering, Electronics and Electrical Parallel Algorithms for VHDL Simulation text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.