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oai:www.ideals.illinois.edu:2142/81920 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

1998 1998 Yew, Pen-Chung Tsai, Jenn-Yuan 2015-09-25T20:21:00Z 2015-09-25T20:21:00Z 10000-01-01 In this thesis we also present the compiler techniques for superthreaded processors. Many existing compiler techniques used in traditional parallelizing compilers for multiprocessors as well as some specific compiler techniques for superthreaded processors are needed for generating superthreaded codes and enhancing parallelism between threads. We evaluate the performance of the superthreaded architecture with a trace-driven, cycle-by-cycle superthreaded processor simulator by using codes transformed by hand and codes generated by our superthreading compiler prototype. The simulation results show that a superthreaded processor can achieve good performance by exploiting both thread-level and instruction-level parallelism in programs. Made available in DSpace on 2015-09-25T20:21:00Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9904609.pdf: 5320832 bytes, checksum: 88589af929d7a618c7d97a2bd619093d (MD5) Previous issue date: 1998 Embargo set by: Seth Robbins for item 83201 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 116 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998. http://hdl.handle.net/2142/81920 (MiAaPQ)AAI9904609 eng Engineering, Electronics and Electrical Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.