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          <dc:contributor>Liu, C.L.</dc:contributor>
          <dc:creator>Saxena, Prashant</dc:creator>
          <dc:date>2015-09-25T20:21:03Z</dc:date>
          <dc:date>2015-09-25T20:21:03Z</dc:date>
          <dc:date>10000-01-01</dc:date>
          <dc:date>1998</dc:date>
          <dc:date>1998</dc:date>
          <dc:description>"Multi-layer technologies present additional challenges to the routing of the nets because the layer assignment can have a large impact on the net delays. Traditional approaches cause the first few nets to monopolize the ""good"" layers. Therefore, they perform poorly under the metric of minimizing the maximum net delay. We propose the use of dynamic area quotas to remedy this problem. Our approach is independent of the routing model and the router used, and works very well in practice."</dc:description>
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  Previous issue date: 1998</dc:description>
          <dc:description>Embargo set by: Seth Robbins for item 83215
Lift date: Forever
Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
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          <dc:identifier>(MiAaPQ)AAI9912369</dc:identifier>
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          <dc:subject>Mathematics</dc:subject>
          <dc:title>The Retiming and Routing of VLSI Circuits</dc:title>
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            <discipline>Computer Science</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
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