2026-09-19T14:38:25Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81947 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Naresh Shanbhag Ibrahim Hajj Ramprasad, Sumant 2015-09-25T20:21:08Z 2015-09-25T20:21:08Z 10000-01-01 1999 1999 We have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for dual-output domino logic that reduces area, dock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Made available in DSpace on 2015-09-25T20:21:08Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9944976.pdf: 6867539 bytes, checksum: cbf332aac70de7eb4438b1d966ca92ff (MD5) Previous issue date: 1999 Embargo set by: Seth Robbins for item 83228 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 136 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999. http://hdl.handle.net/2142/81947 (MiAaPQ)AAI9944976 eng Engineering, Electronics and Electrical Power Estimation and Minimization of Digital Signal Processing Systems text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.