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          <dc:description>U of I Only</dc:description>
          <dc:contributor>Torrellas, Josep</dc:contributor>
          <dc:creator>Kang, Yi</dc:creator>
          <dc:date>2015-09-25T20:21:11Z</dc:date>
          <dc:date>2015-09-25T20:21:11Z</dc:date>
          <dc:date>10000-01-01</dc:date>
          <dc:date>1999</dc:date>
          <dc:date>1999</dc:date>
          <dc:description>Many research issues related to FlexRAM are discussed. We describe the FlexRAM architecture include memory architecture, processor architecture and communication models. The rationales for our architecture design are based on general principles and constraints from the technology and existing computer systems. We address design issues arising from the FlexRAM logical and physical design. We show that it is feasible to implement a FlexRAM chip under current MLD technology by setting up HDL models for a FlexRAM chip and estimating its physical parameters. Evaluations based on high-level simulation are made. Decent speedup numbers are shown that FlexRAM architecture is effective for many data-parallel applications. How to program FlexRAM is also explored and a new programming model for IRAM---Intelligent Memory Operation is suggested. We identify and analyze a range of real applications for FlexRAM, including applications in the domain of data mining, computational biology, decision support and multimedia.</dc:description>
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  Previous issue date: 1999</dc:description>
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Lift date: Forever
Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs</dc:description>
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          <dc:language>eng</dc:language>
          <dc:subject>Engineering, Electronics and Electrical</dc:subject>
          <dc:title>An Intelligent Memory for Data -Parallel Applications</dc:title>
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            <department>Computer Science</department>
            <discipline>Computer Science</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
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