2026-09-22T17:00:54Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/81993 2023-07-11 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Sun-Mo (Steve) Kang Li, Qiao 2015-09-25T20:21:22Z 2015-09-25T20:21:22Z 10000-01-01 2001 2001 ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified. Made available in DSpace on 2015-09-25T20:21:22Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9996651.pdf: 5021310 bytes, checksum: 1677a8e8f5134e6c07ca1447cc9841dd (MD5) Previous issue date: 2001 Embargo set by: Seth Robbins for item 83274 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs U of I Only 121 p. Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001. http://hdl.handle.net/2142/81993 (MiAaPQ)AAI9996651 eng Engineering, Electronics and Electrical Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.