2026-09-22T00:05:11Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/88219 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Pilawa-Podgurski, Robert C. Ho, Aaron Daniel 2015-09-29T20:50:21Z 2015-09-29T20:50:21Z 2017-09-30T09:15:30Z 2015-08 2015-07-21 Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method. Submission published under a 24 month embargo labeled 'U of I only', the embargo will last until 2017-08-01 The student, Aaron Ho, accepted the attached license on 2015-07-20 at 11:34. The student, Aaron Ho, submitted this Thesis for approval on 2015-07-20 at 11:40. This Thesis was approved for publication on 2015-07-21 at 13:32. DSpace SAF Submission Ingestion Package generated from Vireo submission #8561 on 2015-09-29 at 15:00:52 Made available in DSpace on 2015-09-29T20:50:21Z (GMT). No. of bitstreams: 2 HO-THESIS-2015.pdf: 4706258 bytes, checksum: 67b9322a94ae21b4ce3a6b89e8684e88 (MD5) LICENSE.txt: 4205 bytes, checksum: 84b1628e42f758e20957c2a798a5da57 (MD5) Previous issue date: 2015-07-21 Embargo set by: Seth Robbins for item 89499 Lift date: 2017-09-29T20:50:34Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 89499 on 2017-09-30T09:15:30Z. application/pdf http://hdl.handle.net/2142/88219 en Copyright 2015 Aaron Daniel Ho complementary metal–oxide–semiconductor (CMOS) integrated circuits digital control low-power electronics power convertors asymmetric interleaving heterogeneous power rails low voltage complementary metal–oxide–semiconductor (CMOS) power management multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system multiphase power converters multiple supply rails reduced input current ripple size 180 nm Hardware Mathematical model Prototypes Table lookup Time-domain analysis Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails text text 2015-8 Electrical & Computer Engineering Electrical & Computer Engineering University of Illinois at Urbana-Champaign Thesis M.S.