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Schutt-Ainé, José E. Yang, Jerry 2016-03-02T21:06:33Z 2016-03-02T21:06:33Z 2018-03-03T10:15:31Z 2015-11-23 2015-12 The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2017-12-01 The student, Jerry Yang, accepted the attached license on 2015-11-18 at 14:01. The student, Jerry Yang, submitted this Thesis for approval on 2015-11-18 at 15:16. This Thesis was approved for publication on 2015-11-23 at 15:05. DSpace SAF Submission Ingestion Package generated from Vireo submission #8803 on 2016-03-02 at 14:13:12 Made available in DSpace on 2016-03-02T21:06:33Z (GMT). No. of bitstreams: 2 YANG-THESIS-2015.pdf: 16037285 bytes, checksum: 38895b7ae0c186b21ecb9aa4f2f2e979 (MD5) LICENSE.txt: 4207 bytes, checksum: a052190ef8bc330ac85778c71cd68a82 (MD5) Previous issue date: 2015-11-23 Embargo set by: Seth Robbins for item 91407 Lift date: 2018-03-02T21:07:27Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 91407 on 2018-03-03T10:15:31Z. application/pdf http://hdl.handle.net/2142/89204 en Copyright 2015 Jerry Yang High-Speed Data Links SerDes System Design Interconnect Modeling Simulation Measurement Eye Diagram Jitter and Noise Signal Integrity Embedding De-embedding Real-Time Scope System-level design, simulation and measurement for high-speed data links text text Electrical & Computer Engineering Electrical & Computer Engineering University of Illinois at Urbana-Champaign Thesis M.S.