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oai:www.ideals.illinois.edu:2142/90970 2023-07-11 col_2142_5131 com_2142_5130

Chen, Deming Sun, Zelei 2016-07-07T21:18:09Z 2016-07-07T21:18:09Z 2018-07-08T09:15:30Z 2016-04-28 2016-05 High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding method to build the state tran- sition in hardware, and we use the state registers along with main clock signal to generate subclock signals. By analyzing the usage of each register when the nite state machine is in di erent states, we assign the corresponding subclock signals to the register and reduce the unnecessary toggle of the registers when they are not in use. CHStone benchmarks in di erent application categories are used to verify the functionality and test the performance of the designs. The area and power data are measured using downstream commercial state-of-the-art tools during logic synthesis. We gain 5% to 20% dynamic power saving with -6% to 2% area increase. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01 The student, Zelei Sun, accepted the attached license on 2016-04-27 at 13:59. The student, Zelei Sun, submitted this Thesis for approval on 2016-04-27 at 14:06. This Thesis was approved for publication on 2016-04-28 at 13:27. DSpace SAF Submission Ingestion Package generated from Vireo submission #9551 on 2016-07-07 at 14:18:08 Made available in DSpace on 2016-07-07T21:18:09Z (GMT). No. of bitstreams: 2 SUN-THESIS-2016.pdf: 785888 bytes, checksum: 9b3ea516f73571bff5e8a2c5753c8f59 (MD5) LICENSE.txt: 4206 bytes, checksum: 26b10c5016457fc85b511bce9c540b12 (MD5) Previous issue date: 2016-04-28 Embargo set by: Seth Robbins for item 93325 Lift date: 2018-07-07T21:18:16Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 93325 on 2018-07-08T09:15:30Z. application/pdf http://hdl.handle.net/2142/90970 en Copyright 2016 Zelei Sun low power high level synthesis VAST-LP: clock gating in high-level synthesis text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.