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oai:www.ideals.illinois.edu:2142/93044 2023-07-11 col_2142_5131 com_2142_5130

Hanumolu, Pavan Kumar Zhu, Junheng 2016-11-10T18:42:51Z 2016-11-10T18:42:51Z 2018-11-11T10:15:45Z 2016-07-08 2016-08 This thesis explores the time-based techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly digital when implemented in integrated circuits. To better explore their potential area saving benefits, the time-based techniques are implemented to serve the integral control of a type-II PLL. A comprehensive analysis is performed to evaluate the pros and cons of the new techniques. In particular, the noise and power trade-off of having additional oscillators in the system is explained in detail. The analyses are veri ed with a prototype PLL fabricated in 65 nm CMOS technology. The prototype PLL occupies an active area of only 0.0021mm^2 and operates across a supply voltage range of 0.6V to 1.2V providing 0.4-to-2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82mW at 1V supply voltage, and achieves 3.73 ps_rms integrated jitter. This translates to an FoM_J of -226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area. With the application of time-based techniques in clocking circuitry, the proposed time-based integral control PLL shall present a viable alternative to the conventional purely analog or digital PLL architectures. Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-08-01 The student, Junheng Zhu, accepted the attached license on 2016-07-07 at 20:23. The student, Junheng Zhu, submitted this Thesis for approval on 2016-07-07 at 20:34. This Thesis was approved for publication on 2016-07-08 at 10:03. DSpace SAF Submission Ingestion Package generated from Vireo submission #9814 on 2016-11-10 at 12:25:02 Made available in DSpace on 2016-11-10T18:42:51Z (GMT). No. of bitstreams: 2 ZHU-THESIS-2016.pdf: 1993750 bytes, checksum: 5244491c672fdb1f6aa9733c5a6c7767 (MD5) LICENSE.txt: 4208 bytes, checksum: 27d0dfaacec211e5939dc349b274b010 (MD5) Previous issue date: 2016-07-08 Embargo set by: Seth Robbins for item 95467 Lift date: 2018-11-10T18:43:22Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 95467 on 2018-11-11T10:15:45Z. application/pdf http://hdl.handle.net/2142/93044 en Copyright 2016 Junheng Zhu Phase-locked loop Oscillators as Integrators Ring oscillator Current-controlled ring oscillator Pulse-width-modulated control Spur Jitter Phase-locked loop using time-based integral control text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.