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oai:www.ideals.illinois.edu:2142/95466 2023-07-11 col_2142_8888 col_2142_5131 com_2142_8887 com_2142_234 com_2142_5130

Li, Xiuling Li, Xiuling Rogers, John A. Dallesasse, John Feng, Milton Chabak, Kelson D 2017-03-01T16:36:46Z 2017-03-01T16:36:46Z 2019-03-02T10:15:30Z 2016-11-09 2016-12 This dissertation research effort explores new transistor topologies using three-dimensional nanowire (NW)-array channels formed by both bottom-up and top-down synthesis. The bottom-up NW research centers on the Au-catalyzed planar GaAs NW assembly discovered at the University of Illinois Urbana-Champaign (UIUC). The top-down NW research approach involves plasma etching of an emerging wide-bandgap material, Gallium Oxide (Ga2O3), to make arrays of NW channels (or fins) for high-power electronics. Bottom-up AlGaAs/GaAs heterostructure core-shell planar NWs are demonstrated on a wafer scale with excellent yield. Their placement is determined by lithographically patterning an array of Au seeds on semi-insulating GaAs substrate. The GaAs NWs assemble by lateral epitaxy via a vapor-liquid-solid mechanism and align in parallel arrays as a result of the (100) GaAs crystal plane orientation; then, a thin-film AlGaAs layer conforms to the GaAs NWs to form AlGaAs/GaAs NW high-electron mobility channels. Radio frequency (RF) transistors are fabricated and show excellent dc and high-frequency performance. An fmax > 75 GHz with < 2 V supply voltage and ION/IOFF > 104 is measured which is superior compared to carbon-based nanoelectronics and “spin-on III-V NWs”. A comprehensive small-signal model is used to extract the contributing and limiting factors to the RF performance of AlGaAs/GaAs NW-array transistors and predict future performance. Finally, a process is developed to show that III-V NWs on sacrificial epitaxial templates can be transferred to arbitrary substrates. Top-down NWs were formed from Sn-doped Ga2O3 homoepitaxially grown on semi-insulating beta-phase Ga2O3 substrates by metal-organic vapor phase epitaxy. First, conventional planar transistors were fabricated from a sample set to characterize and understand the electrical performance as a function of Sn-doping and epitaxial channel thickness. Second, the high-critical field strength was evaluated to highlight the benefit of using Ga2O3 as a disruptive technology to GaN and SiC. Lastly, the planar transistor results feed into a design for a top-down NW-array transistor. The Ga2O3 NW-arrays were formed by BCl3 plasma etching. A new wrap-gate transistor demonstrates normally-off (enhancement-mode) operation with a high breakdown voltage exceeding 600 V which is superior to any transistor using a 3D channel. Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-12-01 The student, Kelson Chabak, accepted the attached license on 2016-11-08 at 06:21. The student, Kelson Chabak, submitted this Dissertation for approval on 2016-11-08 at 06:23. This Dissertation was approved for publication on 2016-11-09 at 11:40. DSpace SAF Submission Ingestion Package generated from Vireo submission #10223 on 2017-02-28 at 14:36:14 Made available in DSpace on 2017-03-01T16:36:46Z (GMT). No. of bitstreams: 6 CHABAK-DISSERTATION-2016.pdf: 5633629 bytes, checksum: 6c333b4fe2df6bff60d5cfe9011ecb3f (MD5) APL_RightsLink Printable License.pdf: 151632 bytes, checksum: 79e037c33d9e5f5e129433a09b153ef2 (MD5) IEEE_Rightslink_by_Copyright_Clearance_Center.pdf: 142979 bytes, checksum: 5eaef0979c96e42cdeb803730fff2427 (MD5) IOP permissions.pdf: 183469 bytes, checksum: 182ccd7b02b306f1c939ab47ea1af779 (MD5) LICENSE.txt: 4210 bytes, checksum: 25bf4c2c84149ef95822e5bad2b343f6 (MD5) NanoLetters_Rightslink_by_Copyright_Clearance_Center.pdf: 139903 bytes, checksum: 5ee7417327eb8e40034a6ce033f5a608 (MD5) Previous issue date: 2016-11-09 Embargo set by: Seth Robbins for item 98582 Lift date: 2019-03-01T16:37:19Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 98582 on 2019-03-02T10:15:30Z. application/pdf http://hdl.handle.net/2142/95466 en Copyright 2016 Kelson Dean Chabak nanowire transistor High-electron-mobility transistor (HEMT) Fin field effect transistor (finFET) vapor-liquid-solid gallium oxide Metal–oxide–semiconductor field-effect transistor (MOSFET) wrap-gate Three-dimensional field-effect transistors with top-down and bottom-up nanowire-array channels text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Dissertation Ph.D.