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Hanumolu, Pavan Kumar Hanumolu, Pavan Kumar Kumar, Rakesh Schutt-Anie, Jose Shanbhag, Naresh Shu, Guanghua 2017-03-01T17:00:54Z 2017-03-01T17:00:54Z 2019-03-02T10:15:18Z 2016-09-30 2016-12 Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01 The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50. The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42. This Dissertation was approved for publication on 2016-09-30 at 13:20. DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52 Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3 SHU-DISSERTATION-2016.pdf: 13625828 bytes, checksum: 6f7a554d7374c812e5874362c8a3664a (MD5) LICENSE.txt: 4209 bytes, checksum: 9364f41c0fe9c8f540827190943f3d0f (MD5) PROQUEST_LICENSE.txt: 4555 bytes, checksum: a4c0059f8ce4019ea372f3a0c69ce926 (MD5) Previous issue date: 2016-09-30 Embargo set by: Seth Robbins for item 98665 Lift date: 2019-03-01T17:02:22Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98665 Lift date: 2019-03-01T17:03:32Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98665 Lift date: 2019-03-01T17:05:02Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98665 Lift date: 2019-03-01T17:06:55Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 98665 on 2019-03-02T10:15:18Z. application/pdf http://hdl.handle.net/2142/95549 en Copyright 2016, Guanghua Shu Data communication High speed serial link Wireline transceiver Continuous-rate receiver Clock and data recovery Reference-less CDR Digital CDR Jitter peaking Decouple JTRAN/JTOL Phase-rotating PLL Phase interpolator Digitally controlled oscillator (DCO) Supply regulator Active repeater Optical links Energy proportional links Matched source synchronous clocking Rapid on/off clock generator Multiplaying delay-locked loop (MDLL) Dynamic voltage and frequency scaling (DVFS) Rapid on/off (ROO) Alpha-power law model Leakage power Exit latency Energy-efficient wireline transceivers text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Dissertation Ph.D.