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Torrellas, Josep Skarlatos, Dimitrios State 2017-03-01T17:02:02Z 2017-03-01T17:02:02Z 2019-03-02T10:15:07Z 2016-12-05 2016-12 The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this thesis, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01 The student, Dimitrios Skarlatos, accepted the attached license on 2016-12-02 at 14:04. The student, Dimitrios Skarlatos, submitted this Thesis for approval on 2016-12-02 at 14:56. This Thesis was approved for publication on 2016-12-05 at 13:20. DSpace SAF Submission Ingestion Package generated from Vireo submission #10420 on 2017-02-28 at 14:43:11 Made available in DSpace on 2017-03-01T17:02:02Z (GMT). No. of bitstreams: 2 SKARLATOS-THESIS-2016.pdf: 640656 bytes, checksum: 2d600e4f7b03dba0d6cc8243bcaf6638 (MD5) LICENSE.txt: 4216 bytes, checksum: d7b7d07a9b18a00ccdf8c1e595c25a78 (MD5) Previous issue date: 2016-12-05 Embargo set by: Seth Robbins for item 98725 Lift date: 2019-03-01T17:02:22Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98725 Lift date: 2019-03-01T17:03:32Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98725 Lift date: 2019-03-01T17:05:02Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 98725 Lift date: 2019-03-01T17:06:55Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 98725 on 2019-03-02T10:15:07Z. application/pdf http://hdl.handle.net/2142/95609 en Copyright 2016 Dimitrios Skarlatos 3D die-stacking Power management Processor Memory Low-power Energy efficiency Mobile processors Voltage regulation Computer architecture Opportunistic power reassignment between processor and memory in 3D stacks text text Computer Science Computer Science University of Illinois at Urbana-Champaign Thesis M.S.