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Radhakrishnan, Chandrasekhar Shah, Aarti Mahesh Kumar 2017-08-10T19:16:05Z 2017-08-10T19:16:05Z 2017-04-25 2017-05 High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2017-08-10 without embargo terms The student, Aarti Shah, accepted the attached license on 2017-04-25 at 09:20. The student, Aarti Shah, submitted this Thesis for approval on 2017-04-25 at 09:37. This Thesis was approved for publication on 2017-04-25 at 15:00. DSpace SAF Submission Ingestion Package generated from Vireo submission #11032 on 2017-08-10 at 13:46:11 Made available in DSpace on 2017-08-10T19:16:05Z (GMT). No. of bitstreams: 2 SHAH-THESIS-2017.pdf: 1552504 bytes, checksum: 66e87f0e97fa48dafb6b2e111203211d (MD5) LICENSE.txt: 4207 bytes, checksum: 03999c82c954a0f7abe5f47e38b1c02b (MD5) Previous issue date: 2017-04-25 application/pdf http://hdl.handle.net/2142/97465 en Copyright 2017 Aarti Mahesh Kumar Shah Analog-to-digital converters High speed successive approximation register (SAR) Delta-sigma modulators Quantizer Medium resolution successive approximation register (SAR) Time-interleaved successive approximation register (TI SAR) Time-interleaved analog-to-digital converter (ADC) Higher order delta-sigma modulator design Delta-sigma simulink models Successive approximation register analog-to-digital converter (SAR ADC) design Successive-approximation-register based quantizer design for high-speed delta-sigma modulators text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.