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        <identifier>oai:www.ideals.illinois.edu:2142/97496</identifier>
        <datestamp>2023-07-11</datestamp>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:description>Made available in DSpace on 2017-08-10T19:16:15Z (GMT). No. of bitstreams: 2
HUANG-THESIS-2017.pdf: 3198752 bytes, checksum: 355bc51ce749cb631e269cc6116f3c3f (MD5)
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  Previous issue date: 2017-04-26</dc:description>
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          <dc:identifier>http://hdl.handle.net/2142/97496</dc:identifier>
          <dc:language>en</dc:language>
          <dc:rights>Copyright 2017 Sitao Huang</dc:rights>
          <dc:subject>Hardware acceleration</dc:subject>
          <dc:subject>Field-programmable gate array (FPGA)</dc:subject>
          <dc:subject>Forward algorithm</dc:subject>
          <dc:contributor>Chen, Deming</dc:contributor>
          <dc:contributor>Hwu, Wen-Mei M</dc:contributor>
          <dc:creator>Huang, Sitao</dc:creator>
          <dc:date>2017-08-10T19:16:15Z</dc:date>
          <dc:date>2017-08-10T19:16:15Z</dc:date>
          <dc:date>2017-04-26</dc:date>
          <dc:date>2017-05</dc:date>
          <dc:description>With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing data into biologically meaningful information for further clinical analysis and processing. However, given the large volume of the data involved, even modestly complex algorithms would require a prohibitively long time to complete. Hence it is urgent to explore non-conventional implementation platforms to accelerate genomics research. 
In this thesis, we present a Field-Programmable Gate Array (FPGA) accelerated implementation of the Pair Hidden Markov Model (Pair HMM) forward algorithm, the performance bottleneck in the HaplotypeCaller, a critical function in the popular Genome Analysis Toolkit (GATK) variant calling tool. We introduce the PE ring structure which, thanks to the fine-grained parallelism allowed by the FPGA, can be built into various configurations striking a trade-off between Instruction-Level Parallelism (ILP) and data parallelism. We investigate the resource utilization and performance of different configurations. Our solution can achieve a speed-up of up to 487x compared to the C++ baseline implementation on CPU and 1.56x compared to the previous best hardware implementation.</dc:description>
          <dc:description>Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2017-08-10 without embargo terms</dc:description>
          <dc:description>The student, Sitao Huang, accepted the attached license on 2017-04-26 at 15:18.</dc:description>
          <dc:description>The student, Sitao Huang, submitted this Thesis for approval on 2017-04-26 at 15:33.</dc:description>
          <dc:description>This Thesis was approved for publication on 2017-04-26 at 18:18.</dc:description>
          <dc:description>DSpace SAF Submission Ingestion Package generated from Vireo submission #11094 on 2017-08-10 at 13:46:42</dc:description>
          <dc:subject>Pair hidden Markov model (HMM)</dc:subject>
          <dc:subject>Computational genomics</dc:subject>
          <dc:subject>Processing element (PE) ring</dc:subject>
          <dc:title>Hardware acceleration of the pair HMM algorithm for DNA variant calling</dc:title>
          <dc:type>text</dc:type>
          <dc:type>text</dc:type>
          <degree>
            <department>Electrical &amp; Computer Eng</department>
            <discipline>Electrical &amp; Computer Engr</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Thesis</level>
            <name>M.S.</name>
          </degree>
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