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oai:www.ideals.illinois.edu:2142/99289 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Reiman, Chloe Michelle 2018-03-13T15:44:44Z 2018-03-13T15:44:44Z 2017-09-11 2017-12 A custom test board facilitates transmission line pulse (TLP) characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin level response of the integrated circuit (IC) to an IEC 61000-4-2 discharge. Electrostatic discharge (ESD) gun zaps are applied to the test board; simulated and measured waveforms are compared. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-03-13 without embargo terms The student, Chloe Reiman, accepted the attached license on 2017-09-08 at 16:27. The student, Chloe Reiman, submitted this Thesis for approval on 2017-09-08 at 16:36. This Thesis was approved for publication on 2017-09-11 at 15:26. DSpace SAF Submission Ingestion Package generated from Vireo submission #11639 on 2018-03-13 at 10:03:33 Made available in DSpace on 2018-03-13T15:44:44Z (GMT). No. of bitstreams: 3 REIMAN-THESIS-2017.pdf: 2873916 bytes, checksum: 3d2eee85ed7ee89d5142e152e1b19ab6 (MD5) collin_masters.docx: 3278057 bytes, checksum: c97de3c6055616ab3cf686ba1709f47c (MD5) LICENSE.txt: 4210 bytes, checksum: b2ed588e1a6823bf90a09749f2354688 (MD5) Previous issue date: 2017-09-11 application/pdf http://hdl.handle.net/2142/99289 eng Copyright 2017 Chloe Michelle Reiman System-efficient electrostatic discharge (ESD) design (SEED) System Efficient Design Electrostatic discharge (ESD) Electrostatic Discharge Transmission line pulse (TLP) Transmission Line Pulse Evaluation of the practicality of system efficient ESD design text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.