A Linear-Tune Algorithm for Switch-Level Simulation with Race Detection in a Class of MOS VLSI Circuits
Ramachandran, Vijaya
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https://hdl.handle.net/2142/74243
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Title A Linear-Tune Algorithm for Switch-Level Simulation with Race Detection in a Class of MOS VLSI Circuits Author(s) Ramachandran, Vijaya Issue Date 1984-06 Keyword(s) Switch-level simulation Race detection Graph algorithms MOS VLSI Ternary simulation Linear-time simulation NP-completeness Date of Ingest 2015-04-06T20:52:46Z 2017-07-14T23:06:06Z Publisher Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. ACT-48 Type of Resource text Genre of Resource Report (Grant or Annual) Language English Permalink http://hdl.handle.net/2142/74243
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