A Network Flow Approach to the Wafer Scale Integration of VLSI Arrays
Codenotti, Bruno; Tamassia, Roberto
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https://hdl.handle.net/2142/74212
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Title A Network Flow Approach to the Wafer Scale Integration of VLSI Arrays Author(s) Codenotti, Bruno Tamassia, Roberto Issue Date 1985-06 Keyword(s) Network flow VLSI array Fault tolerance Date of Ingest 2015-04-06T20:52:40Z 2017-07-14T23:06:44Z Publisher Applied Computation Theory Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG 85-2222, R-1047, ACT-61 Type of Resource text Genre of Resource Report (Grant or Annual) Language English Permalink http://hdl.handle.net/2142/74212 Sponsor(s)/Grant Number(s) Joint Services Electronics Program / N00014-84-C-0149 Fulbright grant
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