Timing and Area Optimization for Standard-Cell VLSI Circuit Design
Chuang, Weitong; Sapatnekar, Sachin S.; Hajj, Ibrahim N.
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B50-2228_DAC_39.pdf
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https://hdl.handle.net/2142/74481
Description
Title Timing and Area Optimization for Standard-Cell VLSI Circuit Design Author(s) Chuang, Weitong Sapatnekar, Sachin S. Hajj, Ibrahim N. Issue Date 1993-07 Keyword(s) Discrete gate sizing Clock skew optimization Partitioning MOS VLSI circuits Date of Ingest 2015-04-06T20:57:24Z 2017-07-14T23:08:30Z Publisher Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-93-2228, DAC-39 Type of Resource text Genre of Resource Report (Grant or Annual) Language English Permalink http://hdl.handle.net/2142/74481 Sponsor(s)/Grant Number(s) Joint Services Electronics Program / N00014-90-J-1270
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B50-2228_DAC_39.pdf
