A Minimum Area VLSI Architecture for O(logn) Time Sorting
Bilardi, G.; Preparata, F.P.
Permalink
https://hdl.handle.net/2142/74207
Description
Title A Minimum Area VLSI Architecture for O(logn) Time Sorting Author(s) Bilardi, G. Preparata, F.P. Issue Date 1983-11 Keyword(s) VLSI complexity Area-time trade-off Combination sorting Bitonic merging Cube-connected-cycles Mesh Orthogonal trees Optimal algorithms Parallel computation Date of Ingest 2015-04-06T20:52:39Z 2017-07-14T23:13:31Z Publisher Applied Computation Theory Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG 83-2227, R-1006, ACT-45 Type of Resource text Genre of Resource Report (Grant or Annual) Language English Permalink http://hdl.handle.net/2142/74207 Sponsor(s)/Grant Number(s) Joint Services Electronics Program / N00014-79-C-0424 IBM predoctoral Fellowship
Owning Collections
