University of Illinois Urbana-Champaign Academic Units Grainger College of Engineering Coordinated Science Laboratory Report - Coordinated Science Laboratory Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Kriplani, Harish
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https://hdl.handle.net/2142/88626
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Title Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits Author(s) Kriplani, Harish Issue Date 1993-11 Keyword(s) Voltage drop CMOS circuits VLSI circuit reliability Power and ground buses Maximum current Date of Ingest 2015-12-10T23:22:06Z 2017-07-14T23:57:29Z Publisher Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-93-2248, DAC-43 Type of Resource text Genre of Resource Report (Grant or Annual) Language en Permalink http://hdl.handle.net/2142/88626 Sponsor(s)/Grant Number(s) Texas Instruments Inc., the Semiconductor Research Corporation (SRC), and USAF / 92-DP-109 and F30602-92-C-0059
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