University of Illinois Urbana-Champaign

Switch-Level Test Generation for MOS VLSI Circuits

Najm, Farid Nasri

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https://hdl.handle.net/2142/75363

Description

Title
Switch-Level Test Generation for MOS VLSI Circuits
Author(s)
Najm, Farid Nasri
Issue Date
1986-08
Keyword(s)
  • Switch-level
  • MOS VLSI circuits
  • Test generation
  • Fault simulation
  • Physical failures
  • Race conditions
  • Hazards
  • Logic circuits
  • D-algorithm
  • Combinatorial circuits
  • Test vectors
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-86-2223, DAC-2
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75363
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / SRC RSCH 84-06-049-5

Owning Collections

Report - Coordinated Science Laboratory PRIMARY