A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai
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https://hdl.handle.net/2142/75392
Description
Title
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Author(s)
Lim, Chieng-Fai
Issue Date
1991-09
Keyword(s)
Multi-level networks
Optimization
Parallel pruning
Partitioning
Load balancing
Shared memory
Shared-memory
Publisher
Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
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