Timing and Area Optimization for VLSI Circuit and Layout

Chuang, Weitong

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https://hdl.handle.net/2142/88628 Copy

Description

Title

Timing and Area Optimization for VLSI Circuit and Layout

Author(s)

Chuang, Weitong

Issue Date

1994-05

Keyword(s)

• Time-area optimization
• VLSI layout
• Linear programming
• Delay estimation
• Sequential circuits
• Physical design
• Placement
• Gate sizing

Publisher

Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-94-2216, DAC-46

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88628

Sponsor(s)/Grant Number(s)

Joint Services Electronics Program / N00014-90-J-1270

Owning Collections