Partitioning Algorithms for Parallel Circuit Simulation

Yeh, David Ching-kai

Permalink

https://hdl.handle.net/2142/88620 Copy

Description

Title

Partitioning Algorithms for Parallel Circuit Simulation

Author(s)

Yeh, David Ching-kai

Issue Date

1990-06

Keyword(s)

• Direct method parallel circuit simulation node tearing
• Bordered block diagonal forms
• Circuit partitioning
• Multilevel task trees
• Network flows
• Speedup

Date of Ingest

• 2015-12-10T23:22:05Z
• 2017-07-15T01:45:46Z

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-90-2222, DAC-21

Type of Resource

text

Genre of Resource

Report (Grant or Annual)

Language

en

Permalink

http://hdl.handle.net/2142/88620

Sponsor(s)/Grant Number(s)

Texas Instruments Inc.

Owning Collections