Performance Evaluation of Multiple Register Set Architectures and Cache Memories

Eickemeyer, Richard James

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https://hdl.handle.net/2142/88602 Copy

Description

Title

Performance Evaluation of Multiple Register Set Architectures and Cache Memories

Author(s)

Eickemeyer, Richard James

Issue Date

1988-01

Keyword(s)

• Multiple register set architectures
• Memory
• Cache memory
• Performance measurements

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-88-2207, CSG-82

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88602

Sponsor(s)/Grant Number(s)

Semiconductor Research Corp. / 87-DP-109

Owning Collections