Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach

Jiang, Rui

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https://hdl.handle.net/2142/98317 Copy

Description

Title

Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach

Author(s)

Jiang, Rui

Issue Date

2017-07-21

Director of Research (if dissertation) or Advisor (if thesis)

Vasudevan, Shobha

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Electrostatic discharges (ESD)
• Reliability
• Fault modeling
• Mixed-signal simulation
• Fault injection
• Fault detection

Abstract

Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. Therefore, a lot of design work and qualification testings are needed by manufacturers to improve the robustness against the negative effects of ESDs. The trial-and-error based solution implementation has incurred huge costs to companies in terms of labor and time. Despite the ever-increasing effort being devoted to solving ESD-related problems, cases of field returns still happen, and a significant portion can be attributed to soft failure induced by system-level ESD. Despite that, the ESD-induced permanent failures are well-studied and protection mechanisms have proven to work, the studies on ESD-induced soft failures are all on the physical and transistor level. In this thesis, we studied ESD-induced soft failures by first conducting case studies of injecting ESDs into physical devices and observing the application level symptoms of the failures, and then performing simulation-based ESD injections on a well-known instruction-set-architecture. For the first time, we correlated the physical level ESD event to high-level system behavior. We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also demonstrated low-cost protection measures for some of the failures resulted.

Graduation Semester

2017-08

Type of Resource

text

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http://hdl.handle.net/2142/98317

Copyright and License Information

Copyright 2017 Rui Jiang

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