University of Illinois Urbana-Champaign

Dependable design for low-cost ultra-low-power processors

Duwe III, Henry John

Content Files
DUWEIII-DISSERTATION-2017.pdf

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https://hdl.handle.net/2142/99273

Description

Title
Dependable design for low-cost ultra-low-power processors
Author(s)
Duwe III, Henry John
Issue Date
2017-08-15
Director of Research (if dissertation) or Advisor (if thesis)
Kumar, Rakesh
Doctoral Committee Chair(s)
Kumar, Rakesh
Committee Member(s)
  • Chen, Deming
  • Dolecek, Lara
  • Kim, Nam Sung
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Date of Ingest
2018-03-13T15:44:34Z
Keyword(s)
  • Computer architecture
  • Low-power
  • Reliability
  • Security
  • Symbolic simulation
  • Co-analysis
Abstract
Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and security constraints on hardware system design. This dissertation focuses on the architecture and design of dependable ultra-low power computing systems. Specifically, it proposes architecture and design techniques that exploit the unique application and usage characteristics of future computing systems to deliver low power, while meeting the reliability and security constraints of these systems. First, this dissertation considers the challenge of achieving both low power and high reliability in SRAM memories. It proposes both an architectural technique to reduce the overheads of error correction and a technique that uses the nature of error correcting codes to allow lower voltage operation without sacrificing reliability. Next, this dissertation considers low power and low cost. By leveraging the fact that many IoT systems are embedded in nature and will run the same application for their entire lifetime, fine-grained usage characteristics of the hardware-software system can be determined at design time. This dissertation presents a novel hardware-software co-analysis based on symbolic simulation that can determine the possible states of the processor throughout any execution of a specific application. This enables power-gating where more gates are turned off for longer, bespoke processors customized to specific applications, and stricter determination of peak power bounds. Finally, this dissertation considers achieving secure IoT systems at low cost and power overhead. By leveraging the hardware-software co-analysis, this dissertation shows that gate-level information flow security guarantees can be provided without hardware overheads.
Graduation Semester
2017-12
Type of Resource
text
Permalink
http://hdl.handle.net/2142/99273
Copyright and License Information
Copyright 2017 Henry Duwe III

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