Tutorial on direct digital synthesizer structure improvements and static timing analysis
Li, Zexian
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LI-THESIS-2018.pdf
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https://hdl.handle.net/2142/102841
Description
Title
Tutorial on direct digital synthesizer structure improvements and static timing analysis
Author(s)
Li, Zexian
Issue Date
2018-12-13
Director of Research (if dissertation) or Advisor (if thesis)
Schutt-Ainé, José E.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2019-02-07T20:44:24Z
Keyword(s)
DDS, FPGA, STA
Abstract
The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality.
The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.
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LI-THESIS-2018.pdf
