University of Illinois Urbana-Champaign

Software and Hardware Support for Data Intensive Computing

Wei, Mingliang

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Software and Hardware Support for Data Intensive Computing.pdf

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https://hdl.handle.net/2142/11318

Description

Title
Software and Hardware Support for Data Intensive Computing
Author(s)
Wei, Mingliang
Issue Date
2007-04
Keyword(s)
  • data intensive computing
  • computer science
Date of Ingest
2009-04-22T14:50:15Z
Abstract
Many data-intensive applications exhibit poor temporal and spatial locality and perform poorly on commodity processors, due to high cache miss rates. Some due to unsophisticated implementations that do not exploit hardware potentials, others due to their inborn nature of poor data access locality. We address this problem by both software and hardware approaches. We propose programming patterns for Architecture-Level Software Optimizations (ALSO). We choose frequent pattern mining, one very important data-intensive application in the data mining domain, as a case study. We propose a systematic approach by identifying applicable tuning patterns. We show the generality and effectiveness of these optimization strategies by applying them to state-of-the-art implementations. We also study the sensitivity of these optimizations to inputs. Evaluation results show that on a set of datasets, the optimizations yield speedups of up to 2.1; our machine learning technique is effective at selecting the best group of optimizations. In the architectural aspect, we propose a Near-Memory Processor (NMP), a heterogeneous architecture that couples on one chip a commodity microprocessor together with a coprocessor that is designed to run well applications that have poor locality or that require bit manipulations. The coprocessor has a blocked-multithreaded narrow in-order core, and supports vector, streaming, and bit-manipulation computation. It has no caches but has exposed, explicitly addressed fast storage. A common set of primitives supports the use of this storage both for stream buffers and for vector registers. We simulated this coprocessor using a set of 10 benchmarks and kernels that are representative of the applications we expect it to be used for. These codes run much faster, with speedups of up to 18 over a commodity microprocessor, and with a geometric mean of 5.8.
Type of Resource
text
Genre of Resource
Technical Report
Permalink
http://hdl.handle.net/2142/11318
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