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University of Illinois Urbana-Champaign
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A cross-stack, network-centric architectural design for next-generation datacenters
Alian, Mohammad
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https://hdl.handle.net/2142/108449
Description
Title
A cross-stack, network-centric architectural design for next-generation datacenters
Author(s)
Alian, Mohammad
Issue Date
2020-07-07
Director of Research (if dissertation) or Advisor (if thesis)
Kim, Nam Sung
Doctoral Committee Chair(s)
Kim, Nam Sung
Committee Member(s)
Hwu, Wen-mei
Torrellas, Josep
Kumar, Rakesh
Snir, Marc
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Date of Ingest
2020-10-07T20:59:37Z
Keyword(s)
datacenter architecture
near-data processing
near-memory processing
in-network computing
distributed simulation
datacenter network architecture
scale-out processing
Abstract
This thesis proposes a full-stack, cross-layer datacenter architecture based on in-network computing and near-memory processing paradigms. The proposed datacenter architecture is built atop two principles: (1) utilizing commodity, off-the-shelf hardware (i.e., processor, DRAM, and network devices) with minimal changes to their architecture, and (2) providing a standard interface to the programmers for using the novel hardware. More specifically, the proposed datacenter architecture enables a smart network adapter to collectively compress/decompress data exchange between distributed DNN training nodes and assist the operating system in performing aggressive processor power management. It also deploys specialized memory modules in the servers, capable of performing general-purpose computation and network connectivity.
This thesis unlocks the potentials of hardware and operating system co-design in architecting application-transparent, near-data processing hardware for improving datacenter's performance, energy efficiency, and scalability. We evaluate the proposed datacenter architecture using a combination of full-system simulation, FPGA prototyping, and real-system experiments.
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