Testing infrastructure and other considerations in a waferscale processor

Liu, Jingyang

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https://hdl.handle.net/2142/109449 Copy

Description

Title

Testing infrastructure and other considerations in a waferscale processor

Author(s)

Liu, Jingyang

Issue Date

2020-12-09

Director of Research (if dissertation) or Advisor (if thesis)

Kumar, Rakesh

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Date of Ingest

2021-03-05T21:38:24Z

Keyword(s)

• design-for-testability
• waferscale

Abstract

With the breakdown of Dennard scaling, the improvement of computational performance is exploited through parallel computing. Further stimulated by emerging workloads, like machine learning, big data processing, and cloud computing, which are either inherently parallel workloads or easily parallelizable, processor core count continues to increase. Simply cramming more and more processor cores into an ever larger chip is not feasible since the yield of such a large chip can drop dramatically due to manufacturing defects. Complicated large systems with multiple chips and/or packages connected as nodes in a network can deliver massive computation performance but suffer from high communication costs and large area, power, and cooling needed for these systems. Therefore, novel architectures and integration technologies are required to support the growing size of processors. Chiplet-based design is a candidate that can realize large systems while promising high system yield. One part of the system yield, namely the yield of individual dies, highly depends on testing. After introducing the concepts of generic IC testing and an example of testing infrastructure in an ARM-based system, this thesis focuses on the testing infrastructure in a chiplet-based ARM-based waferscale system. Some unique challenges and corresponding solutions in such a waferscale system are addressed. Additionally, verification efforts during this project are detailed, including RTL simulations and FPGA prototyping. The thesis concludes with potential improvement to the author's design as well as future directions.

Graduation Semester

2020-12

Type of Resource

Thesis

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http://hdl.handle.net/2142/109449

Copyright and License Information

Copyright 2020 Jingyang Liu

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