Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS

Tabish, Rohan

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https://hdl.handle.net/2142/113134 Copy

Description

Title

Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS

Author(s)

Tabish, Rohan

Issue Date

2021-07-12

Director of Research (if dissertation) or Advisor (if thesis)

Caccamo, Marco

Doctoral Committee Chair(s)

Caccamo, Marco

Committee Member(s)

• Sha, Lui Raymond
• Nahrstedt, Klara
• Pellizzoni, Rodolfo

Department of Study

Computer Science

Discipline

Computer Science

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

Multicore, MPSoC, Fault Tolerance, Real-Time Computing, Communication, Predictability, Embedded Computing, Embedded Systems, Cyber-Physical Systems

Abstract

The embedded computing revolution is pushing the transition from a single-core processor to a multicore processor where multiple single-core processors are packed into a single chip. With recent hardware advancements and the evolution of new challenging applications in autonomy such as self-driving cars and unmanned aerial vehicles (UAVs), hardware needs to perform immense computation in real-time and at low power. To address such requirements, hardware manufacturers are integrating multiple processing elements such as CPU clusters, GPU, programmable logic (PL), and AI accelerators into a single multiprocessor system-on-chip (MPSoC). One of the common attributes of these high-performance multicore processors and MPSoCs is having a shared memory subsystem. Having shared memory for multicore processors suits well for systems where the average-case performance of the system is the performance metric. However, this is not suitable for safety-critical systems where the developer is interested in the worst-case execution time (WCET) of the task on each processing element in the system. The WCET of a task running on one of the processing elements in these high-performance multicore/MPSoCs changes as we activate more processing elements because of the contention on the shared memory subsystem. This thesis proposes hardware/software solutions for commercial-off-the-shelf (COTS) homogeneous multicore architectures and heterogeneous MPSoCs such that the WCET of the tasks running in these environments can be predictable. Moreover, it presents techniques for inter-core communication, reliability, and streaming of compiler-generated segments on CPU only and CPU + accelerators while ensuring predictability. We categorize COTS-based homogeneous multicore architectures into cache-based and scratchpad-based multicore platforms. For cache-based multicore architectures, the primary sources of contention among the cores include shared last-level cache (LLC), the DRAM memory controller, and the DRAM banks. Strict partitioning of shared resources on such platforms at the operating system (OS) has been proposed in the literature for WCET estimation. However, such partitioning prohibits inter-core communication. This thesis proposes an analyzable inter-core communication mechanism for such platforms by relaxing the strict partitioning assumption. For scratchpad-based multicore architectures, this thesis proposes an SPM-centric OS that takes advantage of the scratchpad memory (SPM), DMA, and the I/O subsystems to implement three-phase execution (load, execute and unload) model such that inter-core interference among the cores can be mitigated. The OS has also been extended to handle the inter/intra-core communication and the bit-flip errors that the ECC modules cannot correct. For the newer generation of heterogeneous MPSoCs that employ processing systems (PS) and programmable logic (PL), the thesis proposes a hardware/software co-design approach that isolates the different criticality domains. Different criticality domains take advantage of hypervisor-level cache-coloring to partition the shared cache. The hypervisor also ensures that high and medium criticality cores always execute the tasks from the SPM in the PL using their dedicated interfaces. The dual-ported SPM, together with the DMA and I/O core, implements the three-phase execution model for high and medium criticality domains. The low-criticality domain executes from DRAM shared by DMA. The work has also been extended to provide the APIs that allow the streaming of segments of large tasks that do not fit into half the SPM for the CPUs. Moreover, an OS framework to support segment streaming across different processing units such as CPU and accelerators with DMA in the PL has also been proposed.

Graduation Semester

2021-08

Type of Resource

Thesis

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http://hdl.handle.net/2142/113134

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Copyright 2021 Rohan Tabish

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