Compiler techniques for enabling general-purpose hardware-agnostic FPGA programming

Ejjeh, Adel

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https://hdl.handle.net/2142/120191 Copy

Description

Title

Compiler techniques for enabling general-purpose hardware-agnostic FPGA programming

Author(s)

Ejjeh, Adel

Issue Date

2022-12-15

Director of Research (if dissertation) or Advisor (if thesis)

• Adve, Vikram S
• Rutenbar, Rob A

Doctoral Committee Chair(s)

Adve, Vikram S

Committee Member(s)

• Chen, Deming
• Nurvitadhi, Eriko

Department of Study

Computer Science

Discipline

Computer Science

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

HLS Compilers, FPGA Compiler, Hardware-Agnostic FPGA Programming

Abstract

Recently, FPGAs have become widely available in heterogeneous systems and public clouds, taking them beyond the traditional audience of hardware designers and making them accessible to the much larger category of software application developers. However, current FPGA programming paradigms are not well suited for this type of developers. Software teams deal with large complex applications, with stringent constraints on development cost, source code portability, code reuse, software security, and rapid development cycles, in addition to performance. These constraints make it difficult to invest extensive time and effort to tune application components for specific hardware targets. In many cases, this translates to an acceptable trade-off of raw performance for improved programmability. As such, software designers would greatly benefit from an end-to-end compiler framework that supports hardware-agnostic programming of FPGAs. It is beyond doubt that hardware-agnostic programming of FPGAs is a difficult problem. While I acknowledge this difficulty, I believe that it is achievable with the following requirements: a) A representation that can efficiently capture parallelism in a hardware-agnostic high-level application and that can easily identify the dataflow between the acceleratable components, b) a compiler and autotuner that can automatically select which hardware-agnostic software components are suitable for acceleration, and tune these components by automatically applying FPGA-specific optimizations, and c) a compiler back end and runtime system that can generate the host and device code and transparently interface the host and device without any extra input from the programmer. In this thesis, I present HPVM2FPGA, a novel end-to-end compiler and autotuning system that can automatically tune hardware-agnostic programs for FPGAs. HPVM2FPGA uses a hardware-agnostic abstraction of parallelism as a compiler intermediate representation (IR), and adds a powerful optimization framework that uses sophisticated, parameterized, compiler optimizations (both FPGA-specific and generic) and design space exploration (DSE) to automatically tune and partition a hardware-agnostic program for a target FPGA. It also adds a code-generation back-end that generates optimized OpenCL code for the FPGA kernels and uses the Intel FPGA SDK for OpenCL (AOC) to synthesize them. The optimization framework includes a variety of compiler optimizations designed to automate some of the manual tuning that is required for FPGAs. These are a combination of loop-level, memory-level, and multi-kernel HPVM DFG optimizations. To make DSE practical for FPGAs, I developed an analytical performance model that estimates the execution time of the optimized input program on the target FPGA, using a loop pipeline latency calculation and a critical path analysis to account for inter-kernel parallelism. This performance model is independent of specific optimizations, and derives its required inputs from a static analysis of the HPVM IR (post-optimizations) and performance metrics generated by the RTL generation stage of AOC. Additionally, I incorporated into the optimization framework automatic partitioning to automatically decide what part of the application to offload to the FPGA for best performance. For that, I use integer linear programming (ILP), taking into account the overall performance and the available resources on the FPGA. This optimization framework is modular and extensible, so that more optimizations can be added relatively easily, and other DSE engines or performance models can be plugged in with minimal effort. I performed an experimental evaluation of HPVM2FPGA, which shows that it can: a) optimize hardware-agnostic, multi-kernel benchmarks achieving up to 33X speedup on an Arria 10 GX FPGA compared to unoptimized baselines, b) match hand-tuned FPGA designs in many cases, and c) provide significant benefits with automatic partitioning when the available FPGA resources are not enough to optimize all the application components. My goal with HPVM2FPGA is to provide a modular and extensible framework for the research community that can act as a basis for hardware-agnostic FPGA programming research, and that could keep on improving with more compiler optimizations, back end code-generation techniques, and performance estimation models/DSE.

Graduation Semester

2023-05

Type of Resource

Thesis

Copyright and License Information

Copyright 2022 Adel Ejjeh

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