Director of Research (if dissertation) or Advisor (if thesis)
Kim, Nam Sung
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Cxl Memory
Computer Architecture
Memory Subsystem
Language
eng
Abstract
This paper presents an efficient solution, EMACS, to count memory accesses for applications utilizing the CXL memory on an FPGA platform. CXL is a promising alternative to the mainstream DDR memory interface that can expand the capacity and bandwidth of a memory system. One type of CXL memory device comes in the form factor of an FPGA with a hard IP, providing extra programmability for its user and thus allowing the implementation of EMACS. EMACS consists of the following 3 key components. 1) A customized hardware logic on the FPGA that fulfills the counting mechanism. 2) A compatible kernel module to handle the communication to the logic. 3) A shell script that automates the control sequence to readily profile the memory accesses for any application. The mechanism and implementation of all three components will be elaborated in this paper, as well as the challenges met in the implementation process. In the end, the outcome of the EMACS tests on several benchmarks will be shown in the form of heatmap graphs.
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