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https://hdl.handle.net/2142/127403
Description
Title
Design of energy-efficient optical receiver
Author(s)
Li, Yongxin
Issue Date
2024-12-06
Director of Research (if dissertation) or Advisor (if thesis)
Hanumolu, Pavan Kumar
Doctoral Committee Chair(s)
Hanumolu, Pavan Kumar
Committee Member(s)
Schutt-Aine, Jose E
Rosenbaum, Elyse
Dragic, Peter D
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
CMOS
Optical Receiver
Duobinary
TIA
Design Methodology
CDR
Time-interleaving
Phase Detector
Abstract
With the demand for data rates growing exponentially, the usage of optical links is expanding at a fast speed. It is important that the optical links are designed to operate most energy-efficiently. In this dissertation, the problem is tacked in two step using two experimentally verified prototype receivers.
The first receiver focuses on the design of the analog front-end (AFE) and measured to achieve an OMA sensitivity of -11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s. The receiver features a low-noise, low-power, high-gain AFE, achieving an input-referred noise current (INRC) of 0.78 µA rms, an averaged INRC density of 6.4 pA/√Hz, consumes 11.4 mW of power, and provides 87 dBΩ transimpedance gain with a 14.2 GHz bandwidth. A systematic design methodology for transimpedance amplifiers (TIAs) was developed based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multi-stage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications.
The second receiver focuses on the design of sampling stage and clock recovery circuit. The receiver features an energy-efficient time-interleaved sampling stage with improved comparator design, and a low-jitter PLL-based CDR with multi-phase spacing error correction scheme. The receiver was tested electrically with 16 Gb/s NRZ data and achieved a JTOL corner over 10 MHz. The energy efficiency is 2.28 pJ/bit in 16 Gb/s NRZ-mode and is predicted to be 1.12 pJ/bit in 32 Gb/s duobinary-mode.
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