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https://hdl.handle.net/2142/127411
Description
Title
32Gb/s PAM4 receiver for die-to-die application
Author(s)
Han, Mingyuan
Issue Date
2024-12-11
Director of Research (if dissertation) or Advisor (if thesis)
Hanumolu, Pavan Kumar
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Die-to-die
Reciever
Interposer
PAM4
Single-to-differential
Single-ended
Comparator
Abstract
This thesis presents a 32Gb/s PAM4 receiver design for short-reach die-to-die application. The proposed PAM4 decoding scheme and the detailed circuit implementation will be the main focus of the thesis. Besides compact de- sign and high energy efficiency, the proposed PAM4 receiver improves the voltage margin seen by the comparator and requires less effort in setting up the reference. This thesis is organized as follows: Section 1 introduces the background of the die-to-die interconnect. Section 2 presents the channel characterization and on-chip channel design. Section 3 shows the proposed architecture while section 4 demonstrates the detailed single-to-differential converter and comparator designs. After that, section 5 shows the receiver top-level architecture, and section 6 concludes the thesis in the end.
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