Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware
Yuan, Chentai
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https://hdl.handle.net/2142/129308
Description
Title
Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware
Author(s)
Yuan, Chentai
Issue Date
2025-05-08
Director of Research (if dissertation) or Advisor (if thesis)
Wang, Dong Kai
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Risc-v Architecture
Microarchitecture Optimization
Graph-based Hardware Modeling
Language
eng
Abstract
As the demand for computing power continues to grow in the modern world, the chip industry has been driven to develop increasingly advanced processors to meet these growing needs. The microarchitecture of modern processors has become very complex, making it more challenging to achieve sustained improvements in performance and efficiency with each new generation. We explore two novel approaches to optimize the efficiency of modern processors: ArchGen, a design-space exploration framework that models processor microarchitecture using graphs, and MESA, a dataflow mapper that performs dynamic binary translation for reconfigurable accelerators. ArchGen introduces a graph representation of hardware architecture to allow rapid design estimations and iterative optimization. MESA, on the other hand, introduces an on-chip hardware controller that monitors running programs on the CPU and offloads them to an accelerator when suitable. This thesis delivers two major contributions: the development of a composable RISC-V vector processor as a base RTL library for ArchGen and the verification of an AXI4 port within MESA. We demonstrate that ArchGen can use our custom RISC-V processor as a baseline for iterative optimization and hardware synthesis. The addition of an AXI4-compliant port to MESA allows it to easily interface with other devices in a system-on-chip. Both methods are evaluated to test their effectiveness and correctness through hardware simulation, synthesis, and performance modeling.
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